General-Purpose I/O (GPIO)
THE PORTS ARE USED TO INTERFACE GLUELESSLY TO OTHER ADSP-BF609 PROCESSORS
WHICH ALSO HAVE THE LINK PORTS PINS BROUGHT OUT.
THE EZ-KIT LITE ENABLES ACCESS TO LINK PORTS 0 AND 1 (REFERRED TO AS LP0
AND LP1 IN SCHEMATICS) VIA CONNECTORS P8 AND J3 , RESPECTIVELY. TWO
TORS. THE PROCESSORS COMMUNICATE VIA THE LINK PORTS, ALL WHILE PERFORMING
INDEPENDENT TASKS ON EACH OF THE EZ-KIT LITE. TO LOOPBACK THE LINK PORT
CONNECTORS ON ONE EZ-KIT LITE OR CONNECT THREE OR MORE EZ-KIT LITES,
OBTAIN A STANDARD, OFF THE SHELF CONNECTOR FROM SAMTEC. FOR MORE INFORMA-
TION, SEE “LINK PORT /JTAG CONNECTORS (J3 AND P8)” ON PAGE 2-25 .
BY DEFAULT, THE EZ-KIT LITE BOOTS FROM THE PARALLEL FLASH MEMORY. LINK
PORT 0 CAN BE SELECTED AS THE BOOT SOURCE BY SETTING THE BOOT MODE SELECT
SWITCH ( SW2 ) TO POSITION 6. SEE “BOOT MODE SELECT SWITCH (SW2)” ON
PAGE 2-19 .
General-Purpose I/O (GPIO)
FOUR LEDS ARE AVAILABLE VIA PROGRAMMABLE PINS PG14 , PG15 , PE14 , AND
PB11 . THE CONNECTIONS ARE ON BY DEFAULT AND CAN BE SHUT OFF THROUGH
SOFTCONFIG.
TWO PUSH BUTTONS ARE AVAILABLE ON PROGRAMMABLE FLAGS PB10 AND PE01 .
THE PUSH BUTTONS ARE CONNECTED TO THE PROCESSOR BY DEFAULT. USE SOFTCON-
FIG TO DISCONNECT THE PUSH BUTTONS. REFER TO “SOFTWARE-CONTROLLED
SWITCHES (SOFTCONFIG)” ON PAGE 2-3 FOR MORE INFORMATION.
JTAG Interface
THE EZ-KIT LITE DESIGN ENABLES A MULTI-PROCESSOR JTAG SESSION USING
CONNECTORS P8 AND J3 . BY DEFAULT, THE BOARD IS SET UP IN SINGLE-PROCESSOR
MODE. IN SINGLE-PROCESSOR MODE, CREATE A CCES SESSION BASED ON A STAND-
ALONE DEBUG AGENT OR AN EXTERNAL EMULATOR. TO USE THE EZ-KIT LITE IN
1-18
ADSP-BF609 EZ-KIT LITE EVALUATION SYSTEM MANUAL
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